%0 Conference Paper %1 conf/vlsic/FerrissPNRPBYSV12 %A Ferriss, Mark A. %A Plouchart, Jean-Olivier %A Natarajan, Arun %A Rylyakov, Alexander V. %A Parker, Benjamin D. %A Babakhani, Aydin %A Yaldiz, Soner %A Sadhu, Bodhisatwa %A Valdes-Garcia, Alberto %A Tierno, José A. %A Friedman, Daniel J. %B VLSIC %D 2012 %I IEEE %K dblp %P 176-177 %T An integral path self-calibration scheme for a 20.1-26.7GHz dual-loop PLL in 32nm SOI CMOS. %U http://dblp.uni-trier.de/db/conf/vlsic/vlsic2012.html#FerrissPNRPBYSV12 %@ 978-1-4673-0848-9

@inproceedings{conf/vlsic/FerrissPNRPBYSV12, added-at = {2022-09-02T00:00:00.000+0200}, author = {Ferriss, Mark A. and Plouchart, Jean-Olivier and Natarajan, Arun and Rylyakov, Alexander V. and Parker, Benjamin D. and Babakhani, Aydin and Yaldiz, Soner and Sadhu, Bodhisatwa and Valdes-Garcia, Alberto and Tierno, José A. and Friedman, Daniel J.}, biburl = {https://www.bibsonomy.org/bibtex/27c7993318decc86ab5ef93afb6b1fb9e/dblp}, booktitle = {VLSIC}, crossref = {conf/vlsic/2012}, ee = {https://doi.org/10.1109/VLSIC.2012.6243847}, interhash = {b2c507cdcf22e908d21d82558ac931dd}, intrahash = {7c7993318decc86ab5ef93afb6b1fb9e}, isbn = {978-1-4673-0848-9}, keywords = {dblp}, pages = {176-177}, publisher = {IEEE}, timestamp = {2024-04-10T15:33:47.000+0200}, title = {An integral path self-calibration scheme for a 20.1-26.7GHz dual-loop PLL in 32nm SOI CMOS.}, url = {http://dblp.uni-trier.de/db/conf/vlsic/vlsic2012.html#FerrissPNRPBYSV12}, year = 2012 }