%0 Conference Paper %1 conf/isqed/RachamallaJRP15 %A Rachamalla, Spandana %A Joseph, Arun %A Rao, Rahul M. %A Pandey, Diwesh %B ISQED %D 2015 %I IEEE %K dblp %P 571-576 %T Virtual logic netlist: Enabling efficient RTL analysis. %U http://dblp.uni-trier.de/db/conf/isqed/isqed2015.html#RachamallaJRP15 %@ 978-1-4799-7581-5

@inproceedings{conf/isqed/RachamallaJRP15, added-at = {2016-08-10T00:00:00.000+0200}, author = {Rachamalla, Spandana and Joseph, Arun and Rao, Rahul M. and Pandey, Diwesh}, biburl = {https://www.bibsonomy.org/bibtex/2a45925c85468e91d9c4ec13ebd4172de/dblp}, booktitle = {ISQED}, crossref = {conf/isqed/2015}, ee = {http://dx.doi.org/10.1109/ISQED.2015.7085490}, interhash = {b391050154a360173b6d54d070c1ddc2}, intrahash = {a45925c85468e91d9c4ec13ebd4172de}, isbn = {978-1-4799-7581-5}, keywords = {dblp}, pages = {571-576}, publisher = {IEEE}, timestamp = {2016-08-11T11:40:25.000+0200}, title = {Virtual logic netlist: Enabling efficient RTL analysis.}, url = {http://dblp.uni-trier.de/db/conf/isqed/isqed2015.html#RachamallaJRP15}, year = 2015 }