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%0 Conference Paper
%1 conf/ssiri/AyavTB10
%A Ayav, Tolga
%A Tuglular, Tugkan
%A Belli, Fevzi
%B SSIRI (Companion)
%D 2010
%I IEEE Computer Society
%K dblp
%P 46-53
%T Towards Test Case Generation for Synthesizable VHDL Programs Using Model Checker.
%U http://dblp.uni-trier.de/db/conf/ssiri/ssiri2010c.html#AyavTB10
%@ 978-0-7695-4087-0
@inproceedings{conf/ssiri/AyavTB10,
added-at = {2017-09-16T00:00:00.000+0200},
author = {Ayav, Tolga and Tuglular, Tugkan and Belli, Fevzi},
biburl = {https://www.bibsonomy.org/bibtex/2b5e7b1a974f9affe02cac2a7effe5005/dblp},
booktitle = {SSIRI (Companion)},
crossref = {conf/ssiri/2010c},
ee = {http://doi.ieeecomputersociety.org/10.1109/SSIRI-C.2010.22},
interhash = {bea518971f24804605198d76cc353713},
intrahash = {b5e7b1a974f9affe02cac2a7effe5005},
isbn = {978-0-7695-4087-0},
keywords = {dblp},
pages = {46-53},
publisher = {IEEE Computer Society},
timestamp = {2019-10-17T18:47:54.000+0200},
title = {Towards Test Case Generation for Synthesizable VHDL Programs Using Model Checker.},
url = {http://dblp.uni-trier.de/db/conf/ssiri/ssiri2010c.html#AyavTB10},
year = 2010
}