%0 Conference Paper %1 conf/vlsid/MajhiJPA95 %A Majhi, Ananta K. %A Jacob, James %A Patnaik, Lalit M. %A Agrawal, Vishwani D. %B VLSI Design %D 1995 %I IEEE Computer Society %K dblp %P 161-165 %T An efficient automatic test generation system for path delay faults in combinational circuits. %U http://dblp.uni-trier.de/db/conf/vlsid/vlsid1995.html#MajhiJPA95 %@ 0-8186-6905-5

@inproceedings{conf/vlsid/MajhiJPA95, added-at = {2023-03-24T00:00:00.000+0100}, author = {Majhi, Ananta K. and Jacob, James and Patnaik, Lalit M. and Agrawal, Vishwani D.}, biburl = {https://www.bibsonomy.org/bibtex/23174a42ff3692407ead483cef098ddeb/dblp}, booktitle = {VLSI Design}, crossref = {conf/vlsid/1995}, ee = {https://doi.ieeecomputersociety.org/10.1109/ICVD.1995.512097}, interhash = {c24c10c629556ad0bb7ea6ee9d6cf280}, intrahash = {3174a42ff3692407ead483cef098ddeb}, isbn = {0-8186-6905-5}, keywords = {dblp}, pages = {161-165}, publisher = {IEEE Computer Society}, timestamp = {2024-04-10T05:46:44.000+0200}, title = {An efficient automatic test generation system for path delay faults in combinational circuits.}, url = {http://dblp.uni-trier.de/db/conf/vlsid/vlsid1995.html#MajhiJPA95}, year = 1995 }