%0 Journal Article %1 Khan_2015 %A Khan, Saddam %A Kadikar, Yogiraj %A Dubey, Shivam %A Kore, Vrushal %D 2015 %I Auricle Technologies, Pvt., Ltd. %J International Journal on Recent and Innovation Trends in Computing and Communication %K Action Algorithm Array Common Divisor Euclid’s Field Gate Greatest Group ISE Joint Programmable Test Xilinx %N 3 %P 1682--1687 %R 10.17762/ijritcc2321-8169.1503171 %T Implementation of 4BIT ALU with GCD %U http://dx.doi.org/10.17762/ijritcc2321-8169.1503171 %V 3 %X This work deals with the implementation of a ALU Processor with GCD using Xilinx ISE 9.1i and Spartan 3 FPGA kit. The GCD processor has been implemented using Euclid’s algorithm. ALU performs arithmetic operations and logical operations. Code is dumped on FPGA kit and output is analyzed. The select line is used to decide the whether which operation to perform either GCD or ALU. The work also involves the simulation of the work on Xilinx ISE 9.1i. The implemented program was simulated and output waveforms were observed. We are using Spartan 3 FPGA board for observing the output. The program is dumped using JTAG( Joint Test Action Group) cable on the FPGA Board.

@article{Khan_2015, abstract = {This work deals with the implementation of a ALU Processor with GCD using Xilinx ISE 9.1i and Spartan 3 FPGA kit. The GCD processor has been implemented using Euclid’s algorithm. ALU performs arithmetic operations and logical operations. Code is dumped on FPGA kit and output is analyzed. The select line is used to decide the whether which operation to perform either GCD or ALU. The work also involves the simulation of the work on Xilinx ISE 9.1i. The implemented program was simulated and output waveforms were observed. We are using Spartan 3 FPGA board for observing the output. The program is dumped using JTAG( Joint Test Action Group) cable on the FPGA Board.}, added-at = {2015-08-13T08:38:12.000+0200}, author = {Khan, Saddam and Kadikar, Yogiraj and Dubey, Shivam and Kore, Vrushal}, biburl = {https://www.bibsonomy.org/bibtex/255c62bb333ad99eff37e6034e4dc251a/ijritcc}, doi = {10.17762/ijritcc2321-8169.1503171}, interhash = {d6d3683ce685304b2fe89c801b8adc5d}, intrahash = {55c62bb333ad99eff37e6034e4dc251a}, journal = {International Journal on Recent and Innovation Trends in Computing and Communication}, keywords = {Action Algorithm Array Common Divisor Euclid’s Field Gate Greatest Group ISE Joint Programmable Test Xilinx}, month = {march}, number = 3, pages = {1682--1687}, publisher = {Auricle Technologies, Pvt., Ltd.}, timestamp = {2015-08-13T08:38:12.000+0200}, title = {Implementation of 4BIT {ALU} with {GCD}}, url = {http://dx.doi.org/10.17762/ijritcc2321-8169.1503171}, volume = 3, year = 2015 }