%0 Conference Paper %1 conf/vlsid/HsiaoJ92 %A Hsiao, Pei-Yung %A Jang, Lih-Der %B VLSI Design %D 1992 %I IEEE Computer Society %K dblp %P 370-371 %T Using a Balanced Quad List Quad Tree to Speed Up a Hierarchical VLSI Compaction Scheme. %U http://dblp.uni-trier.de/db/conf/vlsid/vlsid1992.html#HsiaoJ92 %@ 0-8186-2465-5

@inproceedings{conf/vlsid/HsiaoJ92, added-at = {2023-03-24T00:00:00.000+0100}, author = {Hsiao, Pei-Yung and Jang, Lih-Der}, biburl = {https://www.bibsonomy.org/bibtex/233ca46056894e7ab1945ddb78f6ee662/dblp}, booktitle = {VLSI Design}, crossref = {conf/vlsid/1992}, ee = {https://doi.ieeecomputersociety.org/10.1109/ICVD.1992.658091}, interhash = {e4ecea0b646e4f1b4663b114fa511b64}, intrahash = {33ca46056894e7ab1945ddb78f6ee662}, isbn = {0-8186-2465-5}, keywords = {dblp}, pages = {370-371}, publisher = {IEEE Computer Society}, timestamp = {2024-04-10T05:47:09.000+0200}, title = {Using a Balanced Quad List Quad Tree to Speed Up a Hierarchical VLSI Compaction Scheme.}, url = {http://dblp.uni-trier.de/db/conf/vlsid/vlsid1992.html#HsiaoJ92}, year = 1992 }