%0 Journal Article %1 Goyal_2015 %A Goyal, Shilpa %A Sachdeva, Nitin %A Sachdeva, Tarun %D 2015 %I Auricle Technologies, Pvt., Ltd. %J International Journal on Recent and Innovation Trends in Computing and Communication %K CMOS EDA Phase Tanner Tool Two amplifier margin operational stage %N 4 %P 2255--2260 %R 10.17762/ijritcc2321-8169.1504107 %T Analysis and Design of a Two Stage CMOS OPAMP with 180nm using Miller Compensation Technique %U http://dx.doi.org/10.17762/ijritcc2321-8169.1504107 %V 3 %X With the continuous growing trend towards the reduced supply voltage and transistor channel length, designing of high performance analog integrated circuits such as operational amplifier in CMOS (complementary metal oxide semiconductor) technology becomes more critical. In this paper the two stage CMOS Operational amplifier (op-amp) has been designed using miller compensation technique which operates at 2.5V. Miller compensation technique has been employed with two approaches, first is using single miller compensation capacitor whereas second approach uses single miller compensation capacitor in series with nulling resistor. To achieve increased phase margin which indicate stability of a system, new design has been proposed with the help of second approach. The simulation was performed using TSMC 180nm CMOS process and design has been carried out in tanner EDA tool.

@article{Goyal_2015, abstract = {With the continuous growing trend towards the reduced supply voltage and transistor channel length, designing of high performance analog integrated circuits such as operational amplifier in CMOS (complementary metal oxide semiconductor) technology becomes more critical. In this paper the two stage CMOS Operational amplifier (op-amp) has been designed using miller compensation technique which operates at 2.5V. Miller compensation technique has been employed with two approaches, first is using single miller compensation capacitor whereas second approach uses single miller compensation capacitor in series with nulling resistor. To achieve increased phase margin which indicate stability of a system, new design has been proposed with the help of second approach. The simulation was performed using TSMC 180nm CMOS process and design has been carried out in tanner EDA tool.}, added-at = {2015-08-26T10:18:01.000+0200}, author = {Goyal, Shilpa and Sachdeva, Nitin and Sachdeva, Tarun}, biburl = {https://www.bibsonomy.org/bibtex/285af209177799e6ab44387d24bdbb1fb/ijritcc}, doi = {10.17762/ijritcc2321-8169.1504107}, interhash = {fb0804ee6537495637280688672c3aa9}, intrahash = {85af209177799e6ab44387d24bdbb1fb}, journal = {International Journal on Recent and Innovation Trends in Computing and Communication}, keywords = {CMOS EDA Phase Tanner Tool Two amplifier margin operational stage}, month = {april}, number = 4, pages = {2255--2260}, publisher = {Auricle Technologies, Pvt., Ltd.}, timestamp = {2015-08-26T10:18:01.000+0200}, title = {Analysis and Design of a Two Stage {CMOS} {OPAMP} with 180nm using Miller Compensation Technique}, url = {http://dx.doi.org/10.17762/ijritcc2321-8169.1504107}, volume = 3, year = 2015 }