%0 Conference Paper %1 conf/vlsid/MuroyamaIHY02 %A Muroyama, Masanori %A Ishihara, Tohru %A Hyodo, Akihiko %A Yasuura, Hiroto %B ASP-DAC/VLSI Design %D 2002 %I IEEE Computer Society %K dblp %P 268-273 %T A Power Minimization Technique for Arithmetic Circuits by Cell Selection. %U http://dblp.uni-trier.de/db/conf/vlsid/vlsid2002.html#MuroyamaIHY02 %@ 0-7695-1299-2

@inproceedings{conf/vlsid/MuroyamaIHY02, added-at = {2022-11-14T00:00:00.000+0100}, author = {Muroyama, Masanori and Ishihara, Tohru and Hyodo, Akihiko and Yasuura, Hiroto}, biburl = {https://www.bibsonomy.org/bibtex/2c036bc7bfb2c429fc317a477383deb8a/dblp}, booktitle = {ASP-DAC/VLSI Design}, crossref = {conf/vlsid/2002}, ee = {https://dl.acm.org/doi/10.5555/832284.835376}, interhash = {fbec29ab90ecd95d69a4aea83279e41e}, intrahash = {c036bc7bfb2c429fc317a477383deb8a}, isbn = {0-7695-1299-2}, keywords = {dblp}, pages = {268-273}, publisher = {IEEE Computer Society}, timestamp = {2024-04-10T01:05:13.000+0200}, title = {A Power Minimization Technique for Arithmetic Circuits by Cell Selection.}, url = {http://dblp.uni-trier.de/db/conf/vlsid/vlsid2002.html#MuroyamaIHY02}, year = 2002 }