%0 Conference Paper %1 conf/aspdac/HaqueKHWL13 %A Haque, Mohammad Shihabul %A Kumar, Akash %A Ha, Yajun %A Wu, Qiang %A Luo, Shaobo %B ASP-DAC %D 2013 %I IEEE %K dblp %P 320-325 %T TRISHUL: A single-pass optimal two-level inclusive data cache hierarchy selection process for real-time MPSoCs. %U http://dblp.uni-trier.de/db/conf/aspdac/aspdac2013.html#HaqueKHWL13 %@ 978-1-4673-3029-9

@inproceedings{conf/aspdac/HaqueKHWL13, added-at = {2018-11-24T00:00:00.000+0100}, author = {Haque, Mohammad Shihabul and Kumar, Akash and Ha, Yajun and Wu, Qiang and Luo, Shaobo}, biburl = {https://www.bibsonomy.org/bibtex/20200380cb476b59afe8ecfc64f1321e8/dblp}, booktitle = {ASP-DAC}, crossref = {conf/aspdac/2013}, ee = {https://www.wikidata.org/entity/Q58671727}, interhash = {761f4a87a67f06e26308416bc8d87241}, intrahash = {0200380cb476b59afe8ecfc64f1321e8}, isbn = {978-1-4673-3029-9}, keywords = {dblp}, pages = {320-325}, publisher = {IEEE}, timestamp = {2019-10-17T16:44:50.000+0200}, title = {TRISHUL: A single-pass optimal two-level inclusive data cache hierarchy selection process for real-time MPSoCs.}, url = {http://dblp.uni-trier.de/db/conf/aspdac/aspdac2013.html#HaqueKHWL13}, year = 2013 }