Process Variation (PV) is increasingly threatening the reliability of Networks-on-Chips. Thus, various resilient router designs have been recently proposed and evaluated. However, these evaluations assume random fault distributions, which result in 52%--81% inaccuracy. We propose an accurate circuit-level fault-modeling tool, which can be plugged into any system-level NoC simulator, quantify the system-level impact of PV-induced faults at runtime, pinpoint fault-prone router components that should be protected, and accurately evaluate alternative resilient multi-core designs.
Description
Enabling system-level modeling of variation-induced faults in networks-on-chips
%0 Conference Paper
%1 aisopos2011modeling
%A Aisopos, Konstantinos
%A Chen, Chia-Hsin Owen
%A Peh, Li-Shiuan
%B Proceedings of the 48th Design Automation Conference
%C New York, NY, USA
%D 2011
%I ACM
%K faults modeling noc
%P 930--935
%R 10.1145/2024724.2024931
%T Enabling System-level Modeling of Variation-induced Faults in Networks-on-chips
%U http://doi.acm.org/10.1145/2024724.2024931
%X Process Variation (PV) is increasingly threatening the reliability of Networks-on-Chips. Thus, various resilient router designs have been recently proposed and evaluated. However, these evaluations assume random fault distributions, which result in 52%--81% inaccuracy. We propose an accurate circuit-level fault-modeling tool, which can be plugged into any system-level NoC simulator, quantify the system-level impact of PV-induced faults at runtime, pinpoint fault-prone router components that should be protected, and accurately evaluate alternative resilient multi-core designs.
%@ 978-1-4503-0636-2
@inproceedings{aisopos2011modeling,
abstract = {Process Variation (PV) is increasingly threatening the reliability of Networks-on-Chips. Thus, various resilient router designs have been recently proposed and evaluated. However, these evaluations assume random fault distributions, which result in 52%--81% inaccuracy. We propose an accurate circuit-level fault-modeling tool, which can be plugged into any system-level NoC simulator, quantify the system-level impact of PV-induced faults at runtime, pinpoint fault-prone router components that should be protected, and accurately evaluate alternative resilient multi-core designs.},
acmid = {2024931},
added-at = {2014-02-12T14:34:56.000+0100},
address = {New York, NY, USA},
author = {Aisopos, Konstantinos and Chen, Chia-Hsin Owen and Peh, Li-Shiuan},
biburl = {https://www.bibsonomy.org/bibtex/20594a39f727d1dbb76972e535d216126/eberle18},
booktitle = {Proceedings of the 48th Design Automation Conference},
description = {Enabling system-level modeling of variation-induced faults in networks-on-chips},
doi = {10.1145/2024724.2024931},
interhash = {d72e5b387ed96a4a9f87c02dc53443e4},
intrahash = {0594a39f727d1dbb76972e535d216126},
isbn = {978-1-4503-0636-2},
keywords = {faults modeling noc},
location = {San Diego, California},
numpages = {6},
pages = {930--935},
publisher = {ACM},
series = {DAC '11},
timestamp = {2014-02-12T14:34:56.000+0100},
title = {Enabling System-level Modeling of Variation-induced Faults in Networks-on-chips},
url = {http://doi.acm.org/10.1145/2024724.2024931},
year = 2011
}