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Enabling System-level Modeling of Variation-induced Faults in Networks-on-chips

, , and . Proceedings of the 48th Design Automation Conference, page 930--935. New York, NY, USA, ACM, (2011)
DOI: 10.1145/2024724.2024931

Abstract

Process Variation (PV) is increasingly threatening the reliability of Networks-on-Chips. Thus, various resilient router designs have been recently proposed and evaluated. However, these evaluations assume random fault distributions, which result in 52%--81% inaccuracy. We propose an accurate circuit-level fault-modeling tool, which can be plugged into any system-level NoC simulator, quantify the system-level impact of PV-induced faults at runtime, pinpoint fault-prone router components that should be protected, and accurately evaluate alternative resilient multi-core designs.

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Enabling system-level modeling of variation-induced faults in networks-on-chips

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