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A 45nm dual-port SRAM with write and read capability enhancement at low voltage.
D. P. Wang
,
H. J. Liao
,
H. Yamauchi
,
Y. H. Chen
,
Y. L. Lin
,
S. H. Lin
,
D. C. Liu
,
H. C. Chang
, and
W. Hwang
.
SoCC,
page 211-214.
IEEE,
(
2007
)
@inproceedings{conf/socc/WangLYCLLLCH07, added-at = {2012-05-22T00:00:00.000+0200}, author = {Wang, D. P. and Liao, H. J. and Yamauchi, H. and Chen, Y. H. and Lin, Y. L. and Lin, S. H. and Liu, D. C. and Chang, H. C. and Hwang, W.}, biburl = {http://www.bibsonomy.org/bibtex/20a0df358d0c73ef626dae20d701f6f81/dblp}, booktitle = {SoCC}, crossref = {conf/socc/2007}, ee = {http://dx.doi.org/10.1109/SOCC.2007.4545460}, interhash = {0548160c52779cf6e261530f20dc4bd7}, intrahash = {0a0df358d0c73ef626dae20d701f6f81}, isbn = {978-1-4244-1592-2}, keywords = {dblp}, pages = {211-214}, publisher = {IEEE}, timestamp = {2012-05-22T00:00:00.000+0200}, title = {A 45nm dual-port SRAM with write and read capability enhancement at low voltage.}, url = {http://dblp.uni-trier.de/db/conf/socc/socc2007.html#WangLYCLLLCH07}, year = 2007 }
%0 Conference Paper %1 conf/socc/WangLYCLLLCH07 %A Wang, D. P. %A Liao, H. J. %A Yamauchi, H. %A Chen, Y. H. %A Lin, Y. L. %A Lin, S. H. %A Liu, D. C. %A Chang, H. C. %A Hwang, W. %B SoCC %@ 978-1-4244-1592-2 %D 2007 %I IEEE %K %P 211-214 %T A 45nm dual-port SRAM with write and read capability enhancement at low voltage. %U http://dblp.uni-trier.de/db/conf/socc/socc2007.html#WangLYCLLLCH07
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BibTeX key:
conf/socc/WangLYCLLLCH07
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