%0 Conference Paper %1 conf/vlsic/JiangCKWS16 %A Jiang, Zhewei %A Cerqueira, Joao Pedro %A Kim, Seongjong %A Wang, Qi %A Seok, Mingoo %B VLSI Circuits %D 2016 %I IEEE %K dblp %P 1-2 %T 1.74-µW/ch, 95.3%-accurate spike-sorting hardware based on Bayesian decision. %U http://dblp.uni-trier.de/db/conf/vlsic/vlsic2016.html#JiangCKWS16 %@ 978-1-5090-0635-9

@inproceedings{conf/vlsic/JiangCKWS16, added-at = {2016-09-26T00:00:00.000+0200}, author = {Jiang, Zhewei and Cerqueira, Joao Pedro and Kim, Seongjong and Wang, Qi and Seok, Mingoo}, biburl = {https://www.bibsonomy.org/bibtex/218751f3fb44b1652d2b16d2d6419793d/dblp}, booktitle = {VLSI Circuits}, crossref = {conf/vlsic/2016}, ee = {http://dx.doi.org/10.1109/VLSIC.2016.7573468}, interhash = {020132028b8f9f3fa2d06bb5445dd37f}, intrahash = {18751f3fb44b1652d2b16d2d6419793d}, isbn = {978-1-5090-0635-9}, keywords = {dblp}, pages = {1-2}, publisher = {IEEE}, timestamp = {2016-09-27T11:36:21.000+0200}, title = {1.74-µW/ch, 95.3%-accurate spike-sorting hardware based on Bayesian decision.}, url = {http://dblp.uni-trier.de/db/conf/vlsic/vlsic2016.html#JiangCKWS16}, year = 2016 }