@article{journals/ieicet/OhtomoKNN08,
title = {A PVT Tolerant STM-16 Clock-and-Data Recovery LSI Using an On-Chip Loop-Gain Variation Compensation Architecture in 0.20-µm CMOS/SOI.},
author = {Yusuke Ohtomo and Hiroshi Koizumi and Kazuyoshi Nishimura and Masafumi Nogawa},
journal = {IEICE Transactions},
number = {4},
pages = {655-661},
url = {http://dblp.uni-trier.de/db/journals/ieicet/ieicet91c.html#OhtomoKNN08},
volume = {91-C},
year = {2008},
description = {dblp},
ee = {http://dx.doi.org/10.1093/ietele/e91-c.4.655}, date = {2008-09-16},
keywords = {dblp }
}
::