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dblp's BibTeX entry:  

A 16-Bit by 16-Bit MAC Design Using Fast 5: 3 Compressor Cells.

VLSI Signal Processing, 31(2): 77-89, 2002.
Authors: Ohsang Kwon and Kevin J. Nowka and Earl E. Swartzlander Jr.
URL: http://dblp.uni-trier.de/db/journals/vlsisp/vlsisp31.html#KwonNS02
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| URL | BibTeX  
@article{journals/vlsisp/KwonNS02,
title = {A 16-Bit by 16-Bit MAC Design Using Fast 5: 3 Compressor Cells.},
author = {Ohsang Kwon and Kevin J. Nowka and Earl E. Swartzlander Jr.},
journal = {VLSI Signal Processing},
number = {2},
pages = {77-89},
url = {http://dblp.uni-trier.de/db/journals/vlsisp/vlsisp31.html#KwonNS02},
volume = {31},
year = {2002},
description = {dblp},
ee = {http://dx.doi.org/10.1023/A:1015333103608}, date = {2008-08-06},
keywords = {dblp }
}