%0 Conference Paper %1 conf/iscas/BaeW04 %A Bae, Yong-Cheol %A Wei, Gu-Yeon %B ISCAS (4) %D 2004 %I IEEE %K dblp %P 788-791 %T A mixed PLL/DLL architecture for low jitter clock generation. %U http://dblp.uni-trier.de/db/conf/iscas/iscas2004-4.html#BaeW04 %@ 0-7803-8251-X

@inproceedings{conf/iscas/BaeW04, added-at = {2016-05-20T00:00:00.000+0200}, author = {Bae, Yong-Cheol and Wei, Gu-Yeon}, biburl = {https://www.bibsonomy.org/bibtex/22c0a1a4e41f1d7187beb0adc8a3c55cc/dblp}, booktitle = {ISCAS (4)}, crossref = {conf/iscas/2004}, ee = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=9255}, interhash = {2356bd49c41a0fc1b0092019e9761599}, intrahash = {2c0a1a4e41f1d7187beb0adc8a3c55cc}, isbn = {0-7803-8251-X}, keywords = {dblp}, pages = {788-791}, publisher = {IEEE}, timestamp = {2016-05-21T12:25:01.000+0200}, title = {A mixed PLL/DLL architecture for low jitter clock generation.}, url = {http://dblp.uni-trier.de/db/conf/iscas/iscas2004-4.html#BaeW04}, year = 2004 }