%0 Conference Paper %1 conf/vlsid/BanerjeeDC04 %A Banerjee, Ansuman %A Dasgupta, Pallab %A Chakrabarti, P. P. %B VLSI Design %D 2004 %I IEEE Computer Society %K dblp %P 103-108 %T Formal Verification of Modules under Real Time Environment Constraints. %U http://dblp.uni-trier.de/db/conf/vlsid/vlsid2004.html#BanerjeeDC04 %@ 0-7695-2072-3

@inproceedings{conf/vlsid/BanerjeeDC04, added-at = {2023-03-24T00:00:00.000+0100}, author = {Banerjee, Ansuman and Dasgupta, Pallab and Chakrabarti, P. P.}, biburl = {https://www.bibsonomy.org/bibtex/233ccc7f956989f190f72020f7b39aa58/dblp}, booktitle = {VLSI Design}, crossref = {conf/vlsid/2004}, ee = {https://doi.ieeecomputersociety.org/10.1109/ICVD.2004.1260911}, interhash = {bf15392758a0dc2afe284ae017c6b5d9}, intrahash = {33ccc7f956989f190f72020f7b39aa58}, isbn = {0-7695-2072-3}, keywords = {dblp}, pages = {103-108}, publisher = {IEEE Computer Society}, timestamp = {2024-04-10T04:18:22.000+0200}, title = {Formal Verification of Modules under Real Time Environment Constraints.}, url = {http://dblp.uni-trier.de/db/conf/vlsid/vlsid2004.html#BanerjeeDC04}, year = 2004 }