%0 Journal Article %1 journals/jise/ChenWLHYHL91 %A Chen, Wen-Tsuen %A Wang, Jia-Shung %A Liu, Chia-Cheng %A Horng, Shi-Jinn %A Yang, Chang-Biau %A Huang, Ruey-Zone %A Liaw, Bern-Cherng %D 1991 %J J. Inf. Sci. Eng. %K dblp %N 2 %P 217-235 %T Design of An Integrated Parallel Processing System with Systolic VLSI Chips. %U http://dblp.uni-trier.de/db/journals/jise/jise7.html#ChenWLHYHL91 %V 7

@article{journals/jise/ChenWLHYHL91, added-at = {2021-07-16T00:00:00.000+0200}, author = {Chen, Wen-Tsuen and Wang, Jia-Shung and Liu, Chia-Cheng and Horng, Shi-Jinn and Yang, Chang-Biau and Huang, Ruey-Zone and Liaw, Bern-Cherng}, biburl = {https://www.bibsonomy.org/bibtex/2373a94ec92dbcf46013701d64f33993f/dblp}, ee = {http://www.iis.sinica.edu.tw/page/jise/1991/199106_05.html}, interhash = {06f64a8d8e72e99a9056ca0fc79953aa}, intrahash = {373a94ec92dbcf46013701d64f33993f}, journal = {J. Inf. Sci. Eng.}, keywords = {dblp}, number = 2, pages = {217-235}, timestamp = {2024-04-08T11:21:58.000+0200}, title = {Design of An Integrated Parallel Processing System with Systolic VLSI Chips.}, url = {http://dblp.uni-trier.de/db/journals/jise/jise7.html#ChenWLHYHL91}, volume = 7, year = 1991 }