%0 Conference Paper %1 conf/fpga/GiesenRGD17 %A Giesen, Hans %A Rubin, Raphael %A Gojman, Benjamin %A DeHon, André %B FPGA %D 2017 %E Greene, Jonathan W. %E Anderson, Jason Helge %I ACM %K dblp %P 85-94 %T Quality-Time Tradeoffs in Component-Specific Mapping: How to Train Your Dynamically Reconfigurable Array of Gates with Outrageous Network-delays. %U http://dblp.uni-trier.de/db/conf/fpga/fpga2017.html#GiesenRGD17 %@ 978-1-4503-4354-1

@inproceedings{conf/fpga/GiesenRGD17, added-at = {2017-02-03T00:00:00.000+0100}, author = {Giesen, Hans and Rubin, Raphael and Gojman, Benjamin and DeHon, André}, biburl = {https://www.bibsonomy.org/bibtex/23c3631a067d234ce3e600b6e9b0e93a5/dblp}, booktitle = {FPGA}, crossref = {conf/fpga/2017}, editor = {Greene, Jonathan W. and Anderson, Jason Helge}, ee = {http://dl.acm.org/citation.cfm?id=3026124}, interhash = {094a96aab3218a83222810ef02adac38}, intrahash = {3c3631a067d234ce3e600b6e9b0e93a5}, isbn = {978-1-4503-4354-1}, keywords = {dblp}, pages = {85-94}, publisher = {ACM}, timestamp = {2018-11-07T12:47:38.000+0100}, title = {Quality-Time Tradeoffs in Component-Specific Mapping: How to Train Your Dynamically Reconfigurable Array of Gates with Outrageous Network-delays.}, url = {http://dblp.uni-trier.de/db/conf/fpga/fpga2017.html#GiesenRGD17}, year = 2017 }