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HDL Design for Exa Hertz Clock Based 2e10-1 Exa Bits Per Second (Ebps) PRBS IP Core Generator for Ultra High Speed Wireless Communication Products

, , , and . International Journal on Recent and Innovation Trends in Computing and Communication 3 (1): 264--267 (January 2015)

Abstract

The Design is mainly Intended for High Speed Random Frequency Carrier Wave Generator of 1 Ebps Data Rate using 2e10-1 Tapped PRBS Pattern Sequence. The PRBS is Designed by using LFSR Linear Feed Back Shift Register & XOR Gate with Specific Tapping Points as per CCITT ITU Standards. RTL Design Architecture Implemented by using VHDL &/ Verilog HDL, Programming & Debugging Done by using Spartan III FPGA Kit. Transmission done through this carrier frequency. Propagation Carrier Done either Serially / Parallel lines I/O

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