%0 Conference Paper %1 conf/arc/KhatriHB17 %A Khatri, Abdul Rafay %A Hayek, Ali %A Börcsök, Josef %B ARC %D 2017 %E Wong, Stephan %E Beck, Antonio Carlos Schneider %E Bertels, Koen %E Carro, Luigi %K dblp %P 118-128 %T Hardness Analysis and Instrumentation of Verilog Gate Level Code for FPGA-based Designs. %U http://dblp.uni-trier.de/db/conf/arc/arc2017.html#KhatriHB17 %V 10216 %@ 978-3-319-56258-2

@inproceedings{conf/arc/KhatriHB17, added-at = {2017-05-26T00:00:00.000+0200}, author = {Khatri, Abdul Rafay and Hayek, Ali and Börcsök, Josef}, biburl = {https://www.bibsonomy.org/bibtex/24104ffffd86cd134c6ec9b14dc0729e6/dblp}, booktitle = {ARC}, crossref = {conf/arc/2017}, editor = {Wong, Stephan and Beck, Antonio Carlos Schneider and Bertels, Koen and Carro, Luigi}, ee = {https://doi.org/10.1007/978-3-319-56258-2_11}, interhash = {6b0fb5ce9844679eaa23f8a2efffe232}, intrahash = {4104ffffd86cd134c6ec9b14dc0729e6}, isbn = {978-3-319-56258-2}, keywords = {dblp}, pages = {118-128}, series = {Lecture Notes in Computer Science}, timestamp = {2019-05-15T12:46:23.000+0200}, title = {Hardness Analysis and Instrumentation of Verilog Gate Level Code for FPGA-based Designs.}, url = {http://dblp.uni-trier.de/db/conf/arc/arc2017.html#KhatriHB17}, volume = 10216, year = 2017 }