%0 Conference Paper %1 conf/cse/ReddySVS14 %A Reddy, B. N. Manjunatha %A Sheshagiri, H. N. %A Vijayakumar, B. R. %A S, Shanthala %B CSE %D 2014 %E Liu, Xingang %E Baz, Didier El %E Hsu, Ching-Hsien %E Kang, Kai %E Chen, Weifeng %I IEEE Computer Society %K dblp %P 1868-1871 %T Implementation of Low Power 8-Bit Multiplier Using Gate Diffusion Input Logic. %U http://dblp.uni-trier.de/db/conf/cse/cse2014.html#ReddySVS14 %@ 978-1-4799-7981-3

@inproceedings{conf/cse/ReddySVS14, added-at = {2023-03-24T00:00:00.000+0100}, author = {Reddy, B. N. Manjunatha and Sheshagiri, H. N. and Vijayakumar, B. R. and S, Shanthala}, biburl = {https://www.bibsonomy.org/bibtex/247f5072e34accf92dbb3bdc95359cf1d/dblp}, booktitle = {CSE}, crossref = {conf/cse/2014}, editor = {Liu, Xingang and Baz, Didier El and Hsu, Ching-Hsien and Kang, Kai and Chen, Weifeng}, ee = {https://doi.ieeecomputersociety.org/10.1109/CSE.2014.342}, interhash = {ad78ef6f30f7eca7b3ec362b3574d3ea}, intrahash = {47f5072e34accf92dbb3bdc95359cf1d}, isbn = {978-1-4799-7981-3}, keywords = {dblp}, pages = {1868-1871}, publisher = {IEEE Computer Society}, timestamp = {2024-04-10T04:13:26.000+0200}, title = {Implementation of Low Power 8-Bit Multiplier Using Gate Diffusion Input Logic.}, url = {http://dblp.uni-trier.de/db/conf/cse/cse2014.html#ReddySVS14}, year = 2014 }