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Deterministic clock gating to eliminate wasteful activity due to wrong-path instructions in out-of-order superscalar processors.

Nasir Mohyuddin, Kimish Patel, and Massoud Pedram. ICCD, page 166-172. IEEE, (2009)

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http://dblp.uni-trier.de/db/conf/iccd/iccd2009.html#MohyuddinPP09
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