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Low Voltage and Low Power Divide-By-2/3 Counter Design Using Pass Transistor Logic Circuit Technique.
Yin-Tsung Hwang
, and
Jin-Fa Lin
.
IEEE Trans. VLSI Syst.
20(9):1738-1742
(
2012
)
@article{journals/tvlsi/HwangL12, added-at = {2012-07-18T00:00:00.000+0200}, author = {Hwang, Yin-Tsung and Lin, Jin-Fa}, biburl = {http://www.bibsonomy.org/bibtex/2687a8cb018bf4db8e47dd2a915a68c39/dblp}, ee = {http://dx.doi.org/10.1109/TVLSI.2011.2161598}, interhash = {8b1dc93e65086129702118cd2a1c94b8}, intrahash = {687a8cb018bf4db8e47dd2a915a68c39}, journal = {IEEE Trans. VLSI Syst.}, keywords = {dblp}, number = 9, pages = {1738-1742}, timestamp = {2012-07-18T00:00:00.000+0200}, title = {Low Voltage and Low Power Divide-By-2/3 Counter Design Using Pass Transistor Logic Circuit Technique.}, url = {http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi20.html#HwangL12}, volume = 20, year = 2012 }
%0 Journal Article %1 journals/tvlsi/HwangL12 %A Hwang, Yin-Tsung %A Lin, Jin-Fa %D 2012 %J IEEE Trans. VLSI Syst. %K %N 9 %P 1738-1742 %T Low Voltage and Low Power Divide-By-2/3 Counter Design Using Pass Transistor Logic Circuit Technique. %U http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi20.html#HwangL12 %V 20
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journals/tvlsi/HwangL12
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