| Authors: |
Robert L. Popp
and David J. Montana
and Richard R. Gassner
and Gordon Vidaver
and Suraj Iyer
|
| Tags: |
CAD,
Description
FPGA,
Hardware
Language,
VHDL,
VHSIC
algorithms,
arrays,
automated
circuit
configuration
description
design
design,
evolution,
field
gate
genetic
hardware
languages,
logic,
management,
optimisation,
programmable
programming,
requirements,
software
system
variants
|
| Abstract: |
We have developed a completely automated approach to
hardware design based on integrating three core
technologies into one comprehensive system, namely
genetic programming (GP), the VHSIC Hardware
Description Language (VHDL) and field programmable gate
arrays (FPGAs). Our system uses an automated GP engine,
as opposed to a human designer, to evolve a hardware
design composed of one or more FPGAs that will
maximally achieve an application's software
requirements. Several variants of our system exist;
other variants are currently under development. The
focus of this paper is to describe our original system
design and its most recent revision to date |
@inproceedings{popp:1998:smc,
title = {Automated hardware design using genetic programming,
{VHDL}, and {FPGAs}},
address = {San Diego, CA USA},
author = {Robert L. Popp and David J. Montana and Richard R. Gassner and Gordon Vidaver and Suraj Iyer},
booktitle = {IEEE International Conference on Systems, Man, and
Cybernetics},
month = {11-14 October},
pages = {2184--2189},
publisher = {IEEE},
volume = {3},
year = {1998},
abstract = {We have developed a completely automated approach to
hardware design based on integrating three core
technologies into one comprehensive system, namely
genetic programming (GP), the VHSIC Hardware
Description Language (VHDL) and field programmable gate
arrays (FPGAs). Our system uses an automated GP engine,
as opposed to a human designer, to evolve a hardware
design composed of one or more FPGAs that will
maximally achieve an application's software
requirements. Several variants of our system exist;
other variants are currently under development. The
focus of this paper is to describe our original system
design and its most recent revision to date},
size = {5 pages}, notes = {Inspec Accession Number: 6189463},
keywords = {CAD, Description FPGA, Hardware Language, VHDL, VHSIC algorithms, arrays, automated circuit configuration description design design, evolution, field gate genetic hardware languages, logic, management, optimisation, programmable programming, requirements, software system variants }
}
::