%0 Journal Article %1 journals/esticas/NomuraMTFN16 %A Nomura, Takao %A Mori, Ryo %A Takayanagi, Koji %A Fukuoka, Kazuki %A Nii, Koji %D 2016 %J IEEE J. Emerg. Sel. Topics Circuits Syst. %K dblp %N 3 %P 364-372 %T Design Challenges in 3-D SoC Stacked With a 12.8 GB/s TSV Wide I/O DRAM. %U http://dblp.uni-trier.de/db/journals/esticas/esticas6.html#NomuraMTFN16 %V 6

@article{journals/esticas/NomuraMTFN16, added-at = {2016-09-14T00:00:00.000+0200}, author = {Nomura, Takao and Mori, Ryo and Takayanagi, Koji and Fukuoka, Kazuki and Nii, Koji}, biburl = {https://www.bibsonomy.org/bibtex/26a15f564f14c01510c7f50295c3b1b9b/dblp}, ee = {http://dx.doi.org/10.1109/JETCAS.2016.2547719}, interhash = {7a344076369c5827215e3f9a5b81fdb1}, intrahash = {6a15f564f14c01510c7f50295c3b1b9b}, journal = {IEEE J. Emerg. Sel. Topics Circuits Syst.}, keywords = {dblp}, number = 3, pages = {364-372}, timestamp = {2016-09-15T11:33:07.000+0200}, title = {Design Challenges in 3-D SoC Stacked With a 12.8 GB/s TSV Wide I/O DRAM.}, url = {http://dblp.uni-trier.de/db/journals/esticas/esticas6.html#NomuraMTFN16}, volume = 6, year = 2016 }