%0 Conference Paper %1 conf/fpl/PandeyG06 %A Pandey, Sujan %A Glesner, Manfred %B FPL %D 2006 %I IEEE %K dblp %P 1-6 %T Energy Efficient Statistical On-Chip Communication Bus Synthesis for a Reconfigurable Architecture. %U http://dblp.uni-trier.de/db/conf/fpl/fpl2006.html#PandeyG06 %@ 1-4244-0312-X

@inproceedings{conf/fpl/PandeyG06, added-at = {2017-05-21T00:00:00.000+0200}, author = {Pandey, Sujan and Glesner, Manfred}, biburl = {https://www.bibsonomy.org/bibtex/26b9c91ef6e6bedb23b9473b409a1c9ea/dblp}, booktitle = {FPL}, crossref = {conf/fpl/2006}, ee = {https://doi.org/10.1109/FPL.2006.311210}, interhash = {514f534113467b78dc29b3842e3bd3df}, intrahash = {6b9c91ef6e6bedb23b9473b409a1c9ea}, isbn = {1-4244-0312-X}, keywords = {dblp}, pages = {1-6}, publisher = {IEEE}, timestamp = {2019-10-17T19:14:15.000+0200}, title = {Energy Efficient Statistical On-Chip Communication Bus Synthesis for a Reconfigurable Architecture.}, url = {http://dblp.uni-trier.de/db/conf/fpl/fpl2006.html#PandeyG06}, year = 2006 }