%0 Conference Paper %1 conf/vlsid/SamantaP04 %A Samanta, Debasis %A Pal, Ajit %B VLSI Design %D 2004 %I IEEE Computer Society %K dblp %P 85- %T Synthesis of Low Power High Performance Dual-VT PTL Circuits. %U http://dblp.uni-trier.de/db/conf/vlsid/vlsid2004.html#SamantaP04 %@ 0-7695-2072-3

@inproceedings{conf/vlsid/SamantaP04, added-at = {2023-03-24T00:00:00.000+0100}, author = {Samanta, Debasis and Pal, Ajit}, biburl = {https://www.bibsonomy.org/bibtex/26f7642b525ac46348249aa2fb432f3fe/dblp}, booktitle = {VLSI Design}, crossref = {conf/vlsid/2004}, ee = {https://doi.ieeecomputersociety.org/10.1109/ICVD.2004.1260907}, interhash = {f9106997df62521aaecdc02936b6fd17}, intrahash = {6f7642b525ac46348249aa2fb432f3fe}, isbn = {0-7695-2072-3}, keywords = {dblp}, pages = {85-}, publisher = {IEEE Computer Society}, timestamp = {2024-04-10T04:18:22.000+0200}, title = {Synthesis of Low Power High Performance Dual-VT PTL Circuits.}, url = {http://dblp.uni-trier.de/db/conf/vlsid/vlsid2004.html#SamantaP04}, year = 2004 }