%0 Journal Article %1 journals/jrtip/YinPZ16 %A Yin, Haibing %A Park, Dong Sun %A Zhang, Xiaoyun %D 2016 %J J. Real-Time Image Processing %K dblp %N 3 %P 507-525 %T Buffer structure optimized VLSI architecture for efficient hierarchical integer pixel motion estimation implementation. %U http://dblp.uni-trier.de/db/journals/jrtip/jrtip11.html#YinPZ16 %V 11

@article{journals/jrtip/YinPZ16, added-at = {2016-08-19T00:00:00.000+0200}, author = {Yin, Haibing and Park, Dong Sun and Zhang, Xiaoyun}, biburl = {https://www.bibsonomy.org/bibtex/27526a9be93f2294c4e1449f5766a6f08/dblp}, ee = {http://dx.doi.org/10.1007/s11554-013-0341-6}, interhash = {090c6a5c3fd272268b0afccf655d34bc}, intrahash = {7526a9be93f2294c4e1449f5766a6f08}, journal = {J. Real-Time Image Processing}, keywords = {dblp}, number = 3, pages = {507-525}, timestamp = {2016-08-20T11:33:31.000+0200}, title = {Buffer structure optimized VLSI architecture for efficient hierarchical integer pixel motion estimation implementation.}, url = {http://dblp.uni-trier.de/db/journals/jrtip/jrtip11.html#YinPZ16}, volume = 11, year = 2016 }