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A simulation study on the effectiveness of n-guardring/p-guardring on latchup in 0.8 /spl mu/m CMOS technology.

VLSI Design, : 192-, 1995.
Authors: Varna Puvvada and S. Potla and S. Tamizh Selvam and P. R. Suresh
URL: http://dblp.uni-trier.de/db/conf/vlsid/vlsid1995.html#PuvvadaPSS95
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| URL | BibTeX  
@inproceedings{conf/vlsid/PuvvadaPSS95,
title = {A simulation study on the effectiveness of n-guardring/p-guardring on latchup in 0.8 /spl mu/m CMOS technology.},
author = {Varna Puvvada and S. Potla and S. Tamizh Selvam and P. R. Suresh},
booktitle = {VLSI Design},
crossref = {conf/vlsid/1995},
pages = {192-},
publisher = {IEEE Computer Society},
url = {http://dblp.uni-trier.de/db/conf/vlsid/vlsid1995.html#PuvvadaPSS95},
year = {1995},
description = {dblp},
ee = {http://doi.ieeecomputersociety.org/10.1109/ICVD.1995.512105}, date = {2005-02-25},
keywords = {dblp }
}