Multi-logic-Unit Processor: A Combinational Logic
Circuit Evaluation Engine for Genetic Parallel
Programming
Proceedings of the 8th European Conference on Genetic
Programming, volume 3447 of Lecture Notes in Computer Science, page 167--177. Lausanne, Switzerland, Springer, (30 March - 1 April 2005)Abstract
Genetic Parallel Programming (GPP) is a novel Genetic
Programming paradigm. GPP Logic Circuit Synthesiser
(GPPLCS), is a combinational logic circuit learning
system based on GPP. The GPPLCS comprises a
Multi-Logic-Unit Processor (MLP) which is a hardware
processor built on a Field Programmable Gate Array
(FPGA). The MLP is designed to speed up the evaluation
of genetic parallel programs that represent
combinational logic circuits. Four combinational logic
circuit problems are presented to show the performance
of the hardware-assisted GPPLCS. Experimental results
show that the hardware MLP speeds up evolutions over 10
times. For difficult problems such as the 6-bit
priority selector and the 6-bit comparator, the speedup
ratio can be up to 22.
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