%0 Conference Paper %1 conf/iscas/ChinW94 %A Chin, Shu-Yuan %A Wu, Chung-Yu %B ISCAS %D 1994 %I IEEE %K dblp %P 325-328 %T An Alorithmic Analog-to-Digital Converter with low Ratio-and Gain-Sensitivities and 4N-Clock Conversion Cycle. %U http://dblp.uni-trier.de/db/conf/iscas/iscas1994-5.html#ChinW94 %@ 0-7803-1916-8

@inproceedings{conf/iscas/ChinW94, added-at = {2016-05-23T00:00:00.000+0200}, author = {Chin, Shu-Yuan and Wu, Chung-Yu}, biburl = {https://www.bibsonomy.org/bibtex/2992fe9697591ea46d93ed190e9b19258/dblp}, booktitle = {ISCAS}, crossref = {conf/iscas/1994}, ee = {http://dx.doi.org/10.1109/ISCAS.1994.409373}, interhash = {7703eb622e85fa9e5e853d45948306d6}, intrahash = {992fe9697591ea46d93ed190e9b19258}, isbn = {0-7803-1916-8}, keywords = {dblp}, pages = {325-328}, publisher = {IEEE}, timestamp = {2016-05-24T11:51:44.000+0200}, title = {An Alorithmic Analog-to-Digital Converter with low Ratio-and Gain-Sensitivities and 4N-Clock Conversion Cycle.}, url = {http://dblp.uni-trier.de/db/conf/iscas/iscas1994-5.html#ChinW94}, year = 1994 }