%0 Conference Paper %1 conf/vlsic/ZhangWV16 %A Zhang, Jintao %A Wang, Zhuo %A Verma, Naveen %B VLSI Circuits %D 2016 %I IEEE %K dblp %P 1-2 %T A machine-learning classifier implemented in a standard 6T SRAM array. %U http://dblp.uni-trier.de/db/conf/vlsic/vlsic2016.html#ZhangWV16 %@ 978-1-5090-0635-9

@inproceedings{conf/vlsic/ZhangWV16, added-at = {2016-09-26T00:00:00.000+0200}, author = {Zhang, Jintao and Wang, Zhuo and Verma, Naveen}, biburl = {https://www.bibsonomy.org/bibtex/2a1d0dda483664d9e7b88608866a46995/dblp}, booktitle = {VLSI Circuits}, crossref = {conf/vlsic/2016}, ee = {http://dx.doi.org/10.1109/VLSIC.2016.7573556}, interhash = {bfdcc311ae8677e171ab1079a5dd94db}, intrahash = {a1d0dda483664d9e7b88608866a46995}, isbn = {978-1-5090-0635-9}, keywords = {dblp}, pages = {1-2}, publisher = {IEEE}, timestamp = {2016-09-27T11:36:21.000+0200}, title = {A machine-learning classifier implemented in a standard 6T SRAM array.}, url = {http://dblp.uni-trier.de/db/conf/vlsic/vlsic2016.html#ZhangWV16}, year = 2016 }