%0 Conference Paper %1 conf/aspdac/GargCSK05 %A Garg, Vivek %A Chandrasekhar, Vikram %A Sashikánth, Milagros %A Kamakoti, V. %B ASP-DAC %D 2005 %E Tang, Tingao %I ACM Press %K dblp %P 791-794 %T A novel CLB architecture and circuit packing algorithm for logic-area reduction in SRAM-based FPGAs. %U http://dblp.uni-trier.de/db/conf/aspdac/aspdac2005.html#GargCSK05 %@ 0-7803-8737-6

@inproceedings{conf/aspdac/GargCSK05, added-at = {2020-09-10T00:00:00.000+0200}, author = {Garg, Vivek and Chandrasekhar, Vikram and Sashikánth, Milagros and Kamakoti, V.}, biburl = {https://www.bibsonomy.org/bibtex/2a7913a3dcc001026c6dcda6bf8bee6c0/dblp}, booktitle = {ASP-DAC}, crossref = {conf/aspdac/2005}, editor = {Tang, Tingao}, ee = {https://doi.org/10.1109/ASPDAC.2005.1466462}, interhash = {71372c58d48f001e70c36488e93a0361}, intrahash = {a7913a3dcc001026c6dcda6bf8bee6c0}, isbn = {0-7803-8737-6}, keywords = {dblp}, pages = {791-794}, publisher = {ACM Press}, timestamp = {2020-09-11T12:06:28.000+0200}, title = {A novel CLB architecture and circuit packing algorithm for logic-area reduction in SRAM-based FPGAs.}, url = {http://dblp.uni-trier.de/db/conf/aspdac/aspdac2005.html#GargCSK05}, year = 2005 }