%0 Journal Article %1 journals/tvlsi/KarypisAKS99 %A Karypis, George %A Aggarwal, Rajat %A Kumar, Vipin %A Shekhar, Shashi %D 1999 %J IEEE Trans. Very Large Scale Integr. Syst. %K dblp %N 1 %P 69-79 %T Multilevel hypergraph partitioning: applications in VLSI domain. %U http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi7.html#KarypisAKS99 %V 7

@article{journals/tvlsi/KarypisAKS99, added-at = {2021-11-08T00:00:00.000+0100}, author = {Karypis, George and Aggarwal, Rajat and Kumar, Vipin and Shekhar, Shashi}, biburl = {https://www.bibsonomy.org/bibtex/270d7ff8751613cf70bab0ba47a07a00f/dblp}, ee = {https://www.wikidata.org/entity/Q56171384}, interhash = {2a88a9753d50b7f93696bcfc2fd18fc2}, intrahash = {70d7ff8751613cf70bab0ba47a07a00f}, journal = {IEEE Trans. Very Large Scale Integr. Syst.}, keywords = {dblp}, number = 1, pages = {69-79}, timestamp = {2024-04-08T14:32:25.000+0200}, title = {Multilevel hypergraph partitioning: applications in VLSI domain.}, url = {http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi7.html#KarypisAKS99}, volume = 7, year = 1999 }