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dblp's BibTeX entry:  

A layout-aware physical design method for constructing feasible QCA circuits.

ACM Great Lakes Symposium on VLSI, : 243-248, 2008.
Authors: Mayur Bubna and Sudip Roy and Naresh Shenoy and Subhra Mazumdar
Editors: Vijay Narayanan and Zhiyuan Yan and Enrico Macii and Sanjukta Bhanja
URL: http://dblp.uni-trier.de/db/conf/glvlsi/glvlsi2008.html#BubnaRSM08
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| URL | BibTeX  
@inproceedings{conf/glvlsi/BubnaRSM08,
title = {A layout-aware physical design method for constructing feasible QCA circuits.},
author = {Mayur Bubna and Sudip Roy and Naresh Shenoy and Subhra Mazumdar},
booktitle = {ACM Great Lakes Symposium on VLSI},
crossref = {conf/glvlsi/2008},
editor = {Vijay Narayanan and Zhiyuan Yan and Enrico Macii and Sanjukta Bhanja},
pages = {243-248},
publisher = {ACM},
url = {http://dblp.uni-trier.de/db/conf/glvlsi/glvlsi2008.html#BubnaRSM08},
year = {2008},
description = {dblp},
date = {2008-05-13}, ee = {http://doi.acm.org/10.1145/1366110.1366170}, isbn = {978-1-59593-999-9},
keywords = {dblp }
}