%0 Conference Paper %1 conf/iscas/ChangYH07 %A Chang, Ming-Hung %A Yang, Zong-Xi %A Hwang, Wei %B ISCAS %D 2007 %I IEEE %K dblp %P 1137-1140 %T A 1.9mW Portable ADPLL-based Frequency Synthesizer for High Speed Clock Generation. %U http://dblp.uni-trier.de/db/conf/iscas/iscas2007.html#ChangYH07 %@ 1-4244-0921-7

@inproceedings{conf/iscas/ChangYH07, added-at = {2016-05-20T00:00:00.000+0200}, author = {Chang, Ming-Hung and Yang, Zong-Xi and Hwang, Wei}, biburl = {https://www.bibsonomy.org/bibtex/2b4c0608595487a29ce38da46383608d1/dblp}, booktitle = {ISCAS}, crossref = {conf/iscas/2007}, ee = {http://dx.doi.org/10.1109/ISCAS.2007.378250}, interhash = {50205147f7989cba75ac3885ed816770}, intrahash = {b4c0608595487a29ce38da46383608d1}, isbn = {1-4244-0921-7}, keywords = {dblp}, pages = {1137-1140}, publisher = {IEEE}, timestamp = {2016-05-21T12:14:31.000+0200}, title = {A 1.9mW Portable ADPLL-based Frequency Synthesizer for High Speed Clock Generation.}, url = {http://dblp.uni-trier.de/db/conf/iscas/iscas2007.html#ChangYH07}, year = 2007 }