%0 Journal Article %1 journals/tc/TseS98 %A Tse, John %A Smith, Alan Jay %D 1998 %J IEEE Trans. Computers %K dblp %N 5 %P 509-526 %T CPU Cache Prefetching: Timing Evaluation of Hardware Implementations. %U http://dblp.uni-trier.de/db/journals/tc/tc47.html#TseS98 %V 47

@article{journals/tc/TseS98, added-at = {2015-12-22T00:00:00.000+0100}, author = {Tse, John and Smith, Alan Jay}, biburl = {https://www.bibsonomy.org/bibtex/2c5c600dbffe37f33acd5fc8c78b124fb/dblp}, ee = {http://doi.ieeecomputersociety.org/10.1109/12.677225}, interhash = {e322f2245c4b7cca6d71ab41ad684a22}, intrahash = {c5c600dbffe37f33acd5fc8c78b124fb}, journal = {IEEE Trans. Computers}, keywords = {dblp}, number = 5, pages = {509-526}, timestamp = {2015-12-24T12:03:26.000+0100}, title = {CPU Cache Prefetching: Timing Evaluation of Hardware Implementations.}, url = {http://dblp.uni-trier.de/db/journals/tc/tc47.html#TseS98}, volume = 47, year = 1998 }