%0 Journal Article %1 qian2010worstcase %A Qian, Yue %A Lu, Zhonghai %A Dou, Wenhua %D 2010 %J Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on %K analysis delay noc %N 5 %P 802-815 %R 10.1109/TCAD.2010.2043572 %T Analysis of Worst-Case Delay Bounds for On-Chip Packet-Switching Networks %U http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5452093 %V 29 %X In network-on-chip (NoC), computing worst-case delay bounds for packet delivery is crucial for designing predictable systems but yet an intractable problem. This paper presents an analysis technique to derive per-flow communication delay bound. Based on a network contention model, this technique, which is topology independent, employs network calculus to first compute the equivalent service curve for an individual flow and then calculate its packet delay bound. To exemplify this method, this paper also presents the derivation of a closed-form formula to compute a flow's delay bound under all-to-one gather communication. Experimental results demonstrate that the theoretical bounds are correct and tight.

@article{qian2010worstcase, abstract = {In network-on-chip (NoC), computing worst-case delay bounds for packet delivery is crucial for designing predictable systems but yet an intractable problem. This paper presents an analysis technique to derive per-flow communication delay bound. Based on a network contention model, this technique, which is topology independent, employs network calculus to first compute the equivalent service curve for an individual flow and then calculate its packet delay bound. To exemplify this method, this paper also presents the derivation of a closed-form formula to compute a flow's delay bound under all-to-one gather communication. Experimental results demonstrate that the theoretical bounds are correct and tight.}, added-at = {2014-07-10T15:22:26.000+0200}, author = {Qian, Yue and Lu, Zhonghai and Dou, Wenhua}, biburl = {https://www.bibsonomy.org/bibtex/2c77db564a57be4068adc24d3f8a9ced9/eberle18}, description = {IEEE Xplore Abstract - Analysis of Worst-Case Delay Bounds for On-Chip Packet-Switching Networks}, doi = {10.1109/TCAD.2010.2043572}, interhash = {22a222c91f36c09a0ba4dfd4a9c6db35}, intrahash = {c77db564a57be4068adc24d3f8a9ced9}, issn = {0278-0070}, journal = {Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on}, keywords = {analysis delay noc}, month = may, number = 5, pages = {802-815}, timestamp = {2014-07-10T15:22:26.000+0200}, title = {Analysis of Worst-Case Delay Bounds for On-Chip Packet-Switching Networks}, url = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5452093}, volume = 29, year = 2010 }