%0 Conference Paper %1 conf/islped/MatsunagaKM11 %A Matsunaga, Taeko %A Kimura, Shinji %A Matsunaga, Yusuke %B ISLPED %D 2011 %E Chang, Naehyuck %E Nakamura, Hiroshi %E Inoue, Koji %E Osada, Kenichi %E Poncino, Massimo %I IEEE/ACM %K dblp %P 217-222 %T Power and delay aware synthesis of multi-operand adders targeting LUT-based FPGAs. %U http://dblp.uni-trier.de/db/conf/islped/islped2011.html#MatsunagaKM11 %@ 978-1-61284-660-6

@inproceedings{conf/islped/MatsunagaKM11, added-at = {2012-08-13T00:00:00.000+0200}, author = {Matsunaga, Taeko and Kimura, Shinji and Matsunaga, Yusuke}, biburl = {https://www.bibsonomy.org/bibtex/2cdc8522f84ca4375c3c537c9f9323d41/dblp}, booktitle = {ISLPED}, crossref = {conf/islped/2011}, editor = {Chang, Naehyuck and Nakamura, Hiroshi and Inoue, Koji and Osada, Kenichi and Poncino, Massimo}, ee = {http://portal.acm.org/citation.cfm?id=2016854&CFID=34981777&CFTOKEN=25607807}, interhash = {02b3f2ba046150f9f223811b611044f5}, intrahash = {cdc8522f84ca4375c3c537c9f9323d41}, isbn = {978-1-61284-660-6}, keywords = {dblp}, pages = {217-222}, publisher = {IEEE/ACM}, timestamp = {2012-08-14T11:33:44.000+0200}, title = {Power and delay aware synthesis of multi-operand adders targeting LUT-based FPGAs.}, url = {http://dblp.uni-trier.de/db/conf/islped/islped2011.html#MatsunagaKM11}, year = 2011 }