%0 Conference Paper %1 conf/vlsid/ParasharRMS10 %A Parashar, Karthick %A Rocher, Romuald %A Ménard, Daniel %A Sentieys, Olivier %B VLSI Design %D 2010 %I IEEE Computer Society %K dblp %P 318-323 %T A Hierarchical Methodology for Word-Length Optimization of Signal Processing Systems. %U http://dblp.uni-trier.de/db/conf/vlsid/vlsid2010.html#ParasharRMS10 %@ 978-0-7695-3928-7

@inproceedings{conf/vlsid/ParasharRMS10, added-at = {2016-07-18T00:00:00.000+0200}, author = {Parashar, Karthick and Rocher, Romuald and Ménard, Daniel and Sentieys, Olivier}, biburl = {https://www.bibsonomy.org/bibtex/2d4b57fd1214447e3e4dc4bbcb49ac0f1/dblp}, booktitle = {VLSI Design}, crossref = {conf/vlsid/2010}, ee = {http://doi.ieeecomputersociety.org/10.1109/VLSI.Design.2010.66}, interhash = {db28145bf8debe174dd283a964bc0f81}, intrahash = {d4b57fd1214447e3e4dc4bbcb49ac0f1}, isbn = {978-0-7695-3928-7}, keywords = {dblp}, pages = {318-323}, publisher = {IEEE Computer Society}, timestamp = {2016-07-19T11:41:32.000+0200}, title = {A Hierarchical Methodology for Word-Length Optimization of Signal Processing Systems.}, url = {http://dblp.uni-trier.de/db/conf/vlsid/vlsid2010.html#ParasharRMS10}, year = 2010 }