%0 Conference Paper %1 conf/vlsid/SienickiBAA95 %A Sienicki, James %A Bushnell, Michael L. %A Agrawal, Prathima %A Agrawal, Vishwani D. %B VLSI Design %D 1995 %I IEEE Computer Society %K dblp %P 36-41 %T An asynchronous algorithm for sequential circuit test generation on a network of workstations. %U http://dblp.uni-trier.de/db/conf/vlsid/vlsid1995.html#SienickiBAA95 %@ 0-8186-6905-5

@inproceedings{conf/vlsid/SienickiBAA95, added-at = {2023-03-24T00:00:00.000+0100}, author = {Sienicki, James and Bushnell, Michael L. and Agrawal, Prathima and Agrawal, Vishwani D.}, biburl = {https://www.bibsonomy.org/bibtex/2e12b30fb2966b7eef6bed359d31b9d00/dblp}, booktitle = {VLSI Design}, crossref = {conf/vlsid/1995}, ee = {https://doi.ieeecomputersociety.org/10.1109/ICVD.1995.512074}, interhash = {57d8641747468e4a5cdf352d4a2bc64d}, intrahash = {e12b30fb2966b7eef6bed359d31b9d00}, isbn = {0-8186-6905-5}, keywords = {dblp}, pages = {36-41}, publisher = {IEEE Computer Society}, timestamp = {2024-04-10T05:46:44.000+0200}, title = {An asynchronous algorithm for sequential circuit test generation on a network of workstations.}, url = {http://dblp.uni-trier.de/db/conf/vlsid/vlsid1995.html#SienickiBAA95}, year = 1995 }