%0 Journal Article %1 journals/esticas/OnizawaJHG16 %A Onizawa, Naoya %A Jarollahi, Hooman %A Hanyu, Takahiro %A Gross, Warren J. %D 2016 %J IEEE J. Emerg. Sel. Topics Circuits Syst. %K dblp %N 1 %P 13-24 %T Hardware Implementation of Associative Memories Based on Multiple-Valued Sparse Clustered Networks. %U http://dblp.uni-trier.de/db/journals/esticas/esticas6.html#OnizawaJHG16 %V 6

@article{journals/esticas/OnizawaJHG16, added-at = {2016-03-14T00:00:00.000+0100}, author = {Onizawa, Naoya and Jarollahi, Hooman and Hanyu, Takahiro and Gross, Warren J.}, biburl = {https://www.bibsonomy.org/bibtex/29ff9bf1b4b8465ddac576550f7b4e6b5/dblp}, ee = {http://dx.doi.org/10.1109/JETCAS.2016.2528721}, interhash = {41e78710c3200c5e042e0c651aa62e39}, intrahash = {9ff9bf1b4b8465ddac576550f7b4e6b5}, journal = {IEEE J. Emerg. Sel. Topics Circuits Syst.}, keywords = {dblp}, number = 1, pages = {13-24}, timestamp = {2016-03-15T11:45:18.000+0100}, title = {Hardware Implementation of Associative Memories Based on Multiple-Valued Sparse Clustered Networks.}, url = {http://dblp.uni-trier.de/db/journals/esticas/esticas6.html#OnizawaJHG16}, volume = 6, year = 2016 }