%0 Conference Paper %1 conf/fdl/YueJM16 %A Yue, Daian %A Joloboff, Vania %A Mallet, Frédéric %B FDL %D 2016 %E Drechsler, Rolf %E Wille, Robert %I IEEE %K %P 1-8 %T Flexible runtime verification based on logical clock constraints. %U http://dblp.uni-trier.de/db/conf/fdl/fdl2016.html#YueJM16 %@ 979-10-92279-17-7

@inproceedings{conf/fdl/YueJM16, added-at = {2023-12-12T22:08:11.000+0100}, author = {Yue, Daian and Joloboff, Vania and Mallet, Frédéric}, biburl = {https://www.bibsonomy.org/bibtex/25be53b9b3b58372d32a89ce021b9ba17/admin}, booktitle = {FDL}, crossref = {conf/fdl/2016}, editor = {Drechsler, Rolf and Wille, Robert}, ee = {https://doi.org/10.1109/FDL.2016.7880366}, interhash = {475b7fc85090dfb3fe9e49454e4f32f1}, intrahash = {5be53b9b3b58372d32a89ce021b9ba17}, isbn = {979-10-92279-17-7}, keywords = {}, pages = {1-8}, publisher = {IEEE}, timestamp = {2023-12-12T22:08:11.000+0100}, title = {Flexible runtime verification based on logical clock constraints.}, url = {http://dblp.uni-trier.de/db/conf/fdl/fdl2016.html#YueJM16}, year = 2016 }