%0 Journal Article %1 journals/tvlsi/WangTC16 %A Wang, Dong %A Tan, Xiao Liang %A Chan, Pak Kwong %D 2016 %J IEEE Trans. Very Large Scale Integr. Syst. %K dblp %N 4 %P 1430-1440 %T A Performance-Aware MOSFET Threshold Voltage Measurement Circuit in a 65-nm CMOS. %U http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi24.html#WangTC16 %V 24

@article{journals/tvlsi/WangTC16, added-at = {2020-03-11T00:00:00.000+0100}, author = {Wang, Dong and Tan, Xiao Liang and Chan, Pak Kwong}, biburl = {https://www.bibsonomy.org/bibtex/2be29dc45bd91703d3f57fd38a387ced0/dblp}, ee = {https://doi.org/10.1109/TVLSI.2015.2465841}, interhash = {5f3f0c4ad3799ca718146b1bd9ec1887}, intrahash = {be29dc45bd91703d3f57fd38a387ced0}, journal = {IEEE Trans. Very Large Scale Integr. Syst.}, keywords = {dblp}, number = 4, pages = {1430-1440}, timestamp = {2020-03-12T11:45:17.000+0100}, title = {A Performance-Aware MOSFET Threshold Voltage Measurement Circuit in a 65-nm CMOS.}, url = {http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi24.html#WangTC16}, volume = 24, year = 2016 }