%0 Journal Article %1 journals/tcas/ChenDHMC06 %A Chen, Song %A Dong, Sheqin %A Hong, Xianlong %A Ma, Yuchun %A Cheng, Chung-Kuan %D 2006 %J IEEE Trans. Circuits Syst. II Express Briefs %K dblp %N 8 %P 622-626 %T VLSI Block Placement With Alignment Constraints. %U http://dblp.uni-trier.de/db/journals/tcas/tcasII53.html#ChenDHMC06 %V 53-II

@article{journals/tcas/ChenDHMC06, added-at = {2020-05-27T00:00:00.000+0200}, author = {Chen, Song and Dong, Sheqin and Hong, Xianlong and Ma, Yuchun and Cheng, Chung-Kuan}, biburl = {https://www.bibsonomy.org/bibtex/20bccc784e1e0a2a9b0db3e1ce7463d90/dblp}, ee = {https://doi.org/10.1109/TCSII.2006.876374}, interhash = {609773521a6c0b16253c5d064c129185}, intrahash = {0bccc784e1e0a2a9b0db3e1ce7463d90}, journal = {IEEE Trans. Circuits Syst. II Express Briefs}, keywords = {dblp}, number = 8, pages = {622-626}, timestamp = {2020-05-28T11:53:39.000+0200}, title = {VLSI Block Placement With Alignment Constraints.}, url = {http://dblp.uni-trier.de/db/journals/tcas/tcasII53.html#ChenDHMC06}, volume = {53-II}, year = 2006 }