%0 Conference Paper %1 conf/aspdac/BhardwajCV06 %A Bhardwaj, Sarvesh %A Cao, Yu %A Vrudhula, Sarma B. K. %B ASP-DAC %D 2006 %E Hirose, Fumiyasu %I IEEE %K dblp %P 953-958 %T Statistical leakage minimization through joint selection of gate sizes, gate lengths and threshold voltage. %U http://dblp.uni-trier.de/db/conf/aspdac/aspdac2006.html#BhardwajCV06 %@ 0-7803-9451-8

@inproceedings{conf/aspdac/BhardwajCV06, added-at = {2018-11-06T00:00:00.000+0100}, author = {Bhardwaj, Sarvesh and Cao, Yu and Vrudhula, Sarma B. K.}, biburl = {https://www.bibsonomy.org/bibtex/2766e123e2fad5b36718d9b8f74890521/dblp}, booktitle = {ASP-DAC}, crossref = {conf/aspdac/2006}, editor = {Hirose, Fumiyasu}, ee = {https://doi.org/10.1145/1118299.1118513}, interhash = {69d37ed97404a59ab37cb9c4ab53473b}, intrahash = {766e123e2fad5b36718d9b8f74890521}, isbn = {0-7803-9451-8}, keywords = {dblp}, pages = {953-958}, publisher = {IEEE}, timestamp = {2019-10-17T16:45:43.000+0200}, title = {Statistical leakage minimization through joint selection of gate sizes, gate lengths and threshold voltage.}, url = {http://dblp.uni-trier.de/db/conf/aspdac/aspdac2006.html#BhardwajCV06}, year = 2006 }