%0 Conference Paper %1 conf/parelec/BennerQQ04 %A Benner, Peter %A Quintana-Ortí, Enrique S. %A Quintana-Ortí, Gregorio %B PARELEC %D 2004 %I IEEE Computer Society %K dblp %P 146-151 %T Computing Passive Reduced-Order Models for Circuit Simulation. %U http://dblp.uni-trier.de/db/conf/parelec/parelec2004.html#BennerQQ04 %@ 0-7695-2080-4

@inproceedings{conf/parelec/BennerQQ04, added-at = {2023-03-23T00:00:00.000+0100}, author = {Benner, Peter and Quintana-Ortí, Enrique S. and Quintana-Ortí, Gregorio}, biburl = {https://www.bibsonomy.org/bibtex/241dcf24ca96f6cb1ecf1201d40a1258e/dblp}, booktitle = {PARELEC}, crossref = {conf/parelec/2004}, ee = {https://doi.ieeecomputersociety.org/10.1109/PCEE.2004.21}, interhash = {6ba6f855676483a6f7cfb4bd1481ccb9}, intrahash = {41dcf24ca96f6cb1ecf1201d40a1258e}, isbn = {0-7695-2080-4}, keywords = {dblp}, pages = {146-151}, publisher = {IEEE Computer Society}, timestamp = {2024-04-10T08:18:02.000+0200}, title = {Computing Passive Reduced-Order Models for Circuit Simulation.}, url = {http://dblp.uni-trier.de/db/conf/parelec/parelec2004.html#BennerQQ04}, year = 2004 }