%0 Conference Paper %1 conf/iscas/ChangZZZW07 %A Chang, Xiaotao %A Zhang, Mingming %A Zhang, Ge %A Zhang, Zhimin %A Wang, Jun %B ISCAS %D 2007 %I IEEE %K %P 2120-2123 %T Adaptive Clock Gating Technique for Low Power IP Core in SoC Design. %U http://dblp.uni-trier.de/db/conf/iscas/iscas2007.html#ChangZZZW07 %@ 1-4244-0921-7

@inproceedings{conf/iscas/ChangZZZW07, added-at = {2023-12-13T01:08:27.000+0100}, author = {Chang, Xiaotao and Zhang, Mingming and Zhang, Ge and Zhang, Zhimin and Wang, Jun}, biburl = {https://www.bibsonomy.org/bibtex/2e2b99a3a8f353146801bc10c1c5f872c/admin}, booktitle = {ISCAS}, crossref = {conf/iscas/2007}, ee = {http://dx.doi.org/10.1109/ISCAS.2007.378591}, interhash = {6d563c640c4ea883a4062abdf7f6f44c}, intrahash = {e2b99a3a8f353146801bc10c1c5f872c}, isbn = {1-4244-0921-7}, keywords = {}, pages = {2120-2123}, publisher = {IEEE}, timestamp = {2023-12-13T01:08:27.000+0100}, title = {Adaptive Clock Gating Technique for Low Power IP Core in SoC Design.}, url = {http://dblp.uni-trier.de/db/conf/iscas/iscas2007.html#ChangZZZW07}, year = 2007 }