Inproceedings,
Hardware architecture for lowering the error floor of LTE turbo codes.
T. Tonnellier, C. Leroux, B. Gal, C. Jégo, B. Gadat, and N. Wambeke.DASIP, page 107-112. IEEE, (2016)
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- BibTeX key
- conf/dasip/TonnellierLGJGW16
- entry type
- inproceedings
- booktitle
- DASIP
- year
- 2016
- pages
- 107-112
- publisher
- IEEE
- crossref
- conf/dasip/2016
- ee
- https://doi.org/10.1109/DASIP.2016.7853805
- isbn
- 979-1-0922-7915-3
- url
- http://dblp.uni-trier.de/db/conf/dasip/dasip2016.html#TonnellierLGJGW16
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- please select -%0 Conference Paper
%1 conf/dasip/TonnellierLGJGW16
%A Tonnellier, Thibaud
%A Leroux, Camille
%A Gal, Bertrand Le
%A Jégo, Christophe
%A Gadat, Benjamin
%A Wambeke, Nicolas Van
%B DASIP
%D 2016
%I IEEE
%K dblp
%P 107-112
%T Hardware architecture for lowering the error floor of LTE turbo codes.
%U http://dblp.uni-trier.de/db/conf/dasip/dasip2016.html#TonnellierLGJGW16
%@ 979-1-0922-7915-3
@inproceedings{conf/dasip/TonnellierLGJGW16,
added-at = {2019-10-19T00:00:00.000+0200},
author = {Tonnellier, Thibaud and Leroux, Camille and Gal, Bertrand Le and Jégo, Christophe and Gadat, Benjamin and Wambeke, Nicolas Van},
biburl = {https://www.bibsonomy.org/bibtex/2431cd3558773bda9de8305c7a8cbdbff/dblp},
booktitle = {DASIP},
crossref = {conf/dasip/2016},
ee = {https://doi.org/10.1109/DASIP.2016.7853805},
interhash = {7e7b6f4d0bd0ceda57b537217cfa41e7},
intrahash = {431cd3558773bda9de8305c7a8cbdbff},
isbn = {979-1-0922-7915-3},
keywords = {dblp},
pages = {107-112},
publisher = {IEEE},
timestamp = {2019-10-22T13:46:46.000+0200},
title = {Hardware architecture for lowering the error floor of LTE turbo codes.},
url = {http://dblp.uni-trier.de/db/conf/dasip/dasip2016.html#TonnellierLGJGW16},
year = 2016
}