%0 Journal Article %1 journals/tcad/BoubezariCKN99 %A Boubezari, Samir %A Cerny, Eduard %A Kaminska, Bozena %A Nadeau-Dostie, Benoit %D 1999 %J IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. %K dblp %N 9 %P 1327-1340 %T Testability analysis and test-point insertion in RTL VHDL specifications for scan-based BIST. %U http://dblp.uni-trier.de/db/journals/tcad/tcad18.html#BoubezariCKN99 %V 18

@article{journals/tcad/BoubezariCKN99, added-at = {2020-09-24T00:00:00.000+0200}, author = {Boubezari, Samir and Cerny, Eduard and Kaminska, Bozena and Nadeau-Dostie, Benoit}, biburl = {https://www.bibsonomy.org/bibtex/2b79e61b1e6a8d0f4035b5dbe24ed1e5f/dblp}, ee = {https://doi.org/10.1109/43.784124}, interhash = {80bd1de37129f2f50c2ac482747f07a0}, intrahash = {b79e61b1e6a8d0f4035b5dbe24ed1e5f}, journal = {IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.}, keywords = {dblp}, number = 9, pages = {1327-1340}, timestamp = {2020-09-25T11:50:48.000+0200}, title = {Testability analysis and test-point insertion in RTL VHDL specifications for scan-based BIST.}, url = {http://dblp.uni-trier.de/db/journals/tcad/tcad18.html#BoubezariCKN99}, volume = 18, year = 1999 }